It is commonly recognized that electrical characteristics of transistors and interconnects are not the same for different chips and even for the same chip at different periods of time or chip locations. Variation of electrical characteristics can be due to variation of process parameters, changing of environmental conditions and even chip age (e.g., Hot Carriers Injections, Negative Bias Temperature Instability, electromigration, and so forth).
The variation of electrical characteristics results in variations of gate timing characteristics. The traditional conservative way to handle these variations is to consider so-called process corners at which the gates have the worst combinations of delays. Then chips are designed so that they can properly function at all process corners assuming that as a result they will function at any other combination of gate delays.
However, with decreasing transistor size and interconnect width, the variation of electrical characteristics is becoming proportionally larger. Therefore, the approach to design for process corners results in too conservative and non-optimal designs because most design efforts and chip resources are spent to make chips function at very low-probability combinations of electrical characteristics.
An alternative approach to designing chips is to consider actual statistical characteristics of process parameter variations and use them to compute statistical characteristics of a designed circuit. For digital circuits, this approach is known as statistical timing analysis. There are several varieties of statistical timing analysis.
One of the most useful for circuit analysis and optimization is parameterized statistical static timing analysis (SSTA). According to this technique, gate delays and signal arrival times are represented as functions of process parameters. All the parameters are assumed independent. This assumption significantly simplifies the analysis but does not limit its applicability because independence can be obtained by a principal component analysis technique. Using this representation, the parameterized SSTA computes a statistical approximation of the circuit timing characteristics (arrival and required arrival times, delay, timing slack) as functions of the same parameters.
The parameterized SSTA can be either path-based or block-based. Path-based statistical SSTA analyzes each signal propagation path separately and computes the probability distribution for circuit delay as the probabilistic maximum of all paths delays. Usually this requires enumeration of all signal propagation paths and integration in the space of parameters variations, which can be an inefficient computational procedure.
A more efficient technique of parameterized SSTA is so-called block-based SSTA. This technique is very similar to traditional deterministic static timing analysis (STA). For example, block-based SSTA computes signal arrival times (or signal required arrival times) as functions of process parameters for each circuit node in their topological order similarly to propagating arrival times by a deterministic STA. This type of timing analysis lends itself to incremental operation, whereby after a change of the circuit is made, timing can be queried efficiently.
Block-based SSTA assumes that all parameters variations have normal Gaussian distributions and that gate and wire delays depend on parameters linearly. Linear and Gaussian assumptions are very convenient for parameterized SSTA because it is possible to use approximate analytical formulae for computing canonical forms of arrival times. The use of analytical formulae can make parameterized SSTA fast, which is important for implementing a statistical approach in circuit synthesis and optimization. Unfortunately, the use of statistical parameterized SSTA to model process variation can be computationally inefficient at times and provide overly pessimistic results.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.